1. Field of the Invention
The present invention relates to a silicon single crystal wafer for IGBT used in the production of insulated gate bipolar transistors (IGBT), and a method for manufacturing a silicon single crystal wafer for IGBT.
The present application claims priority from Japanese Patent Application No. 2006-043572, filed on Feb. 21, 2006 and Japanese Patent Application No. 2007-034536, filed on Feb. 15, 2007, the contents of which are incorporated herein by reference.
2. Background Art
Insulated gate bipolar transistors (IGBT) are gate voltage-driven switching devices suitable for controlling high levels of electrical power, and are used in applications such as the inverters of trains, hybrid vehicles, air-conditioning equipment and refrigerators. IGBT are provided with three electrodes consisting of an emitter, a collector and a gate, and as a result of applying a voltage to the gate formed on the front surface of the device through an insulating oxide film, current between the emitter on the front surface of the device and the collector on the rear surface is controlled.
As described above, since IGBT are devices for controlling current with a gate insulated with an oxide film, the integrity of the gate oxide film (referred to as gate oxide integrity and abbreviated as GOI) is important. If a defect is contained in a silicon single crystal wafer, that defect ends up being incorporated into the gate oxide film, thereby causing a dielectric breakdown of the oxide film.
In addition, since IGBT are not devices that use only the vicinity of the wafer surface in the horizontal direction in the manner of memory devices and other LSI, but rather devices that use the wafer in the vertical direction, the characteristics thereof are affected by the bulk quality of the wafer. Recombination lifetime and resistivity are particularly important qualities. Since recombination lifetime decreases due to the presence of crystal defects in a wafer, it is important to control the device process so that crystal defects do not occur at any point in the process. Uniformity and stability are required for resistivity, and it is important that resistivity does not change within a wafer surface or between wafers, namely that resistivity is uniform even in the direction of length of silicon ingots and does not change through the device heating process.
In addition, epitaxial wafers (referred to as epiwafers) are used as wafers for so-called punch through (PT) type IGBT in which a depletion layer contacts the collector side when current flow is off. However, PT-type IGBT have the problem of high cost due to the use of epiwafers. In addition, switching loss increases at high temperatures to control lifetime. Consequently, on-voltage decreases at high temperatures and current concentrates in a specific device during parallel use, thereby causing damage.
In order to overcome the shortcomings of PT-type wafers, non-punch-through (NPT) type IGBT have been developed in which the depletion layer does not contact the collector side when the current is off. More recently, field stop (FS) IGBT are being produced having lower on voltage and lower switching loss by employing a trench gate structure and forming an FS layer on the collector side. Wafers having a diameter of 150 mm or less cut out from silicon single crystals grown by the FZ method (referred to as FZ wafers) have conventionally been used as wafers for NPT-type and FS-type IGBT.
Although FZ wafers are less expensive than epiwafers, wafers are required to have a large diameter in order to further lower IGBT production costs. However, it is extremely difficult to grow single crystals having a diameter larger than 150 mm by the FZ method, and even if they were able to be produced, it would be difficult to provide them at a low price and in stable supply.
Therefore, we attempted to manufacture a silicon single crystal wafer for IGBT by the Czochralski method (CZ method) capable of easily growing large-diameter crystals.
Each of the technologies described in the following Patent Documents 1 to 3 explained below are used for the purpose of reducing defects within wafers. Patent Document 1 discloses a silicon single crystal wafer doped with nitrogen in which the entire surface is composed of an N region and the interstitial oxygen concentration is 8 ppma or less, or doped with nitrogen in which at least void defects and dislocation clusters have been eliminated from the entire surface and the interstitial oxygen concentration is 8 ppma or less.
In addition, Patent Document 2 discloses a method for manufacturing a silicon single crystal which is pulled using the Czochralski method during doping with oxygen and nitrogen, wherein the single crystal is doped with oxygen at a concentration of less than 6.5×1017 atoms/cm3 and nitrogen at a concentration of more than 5×1013 atoms/cm3 during pulling.
Moreover, Patent Document 3 discloses a silicon semiconductor substrate grown from a melt containing nitrogen using the Czochralski method, containing nitrogen at a concentration of 2×1014 to 2×1016 atoms/cm3 and oxygen at a concentration of 7×1017 atoms/cm3 or less in which each type of surface defect density is such that FPD≦0.1 defect/cm2, SEPD≦0.1 defect/cm2 and OSF≦0.1 defect/cm2, the internal defect density is such that LSTD≦1×105 defects/cm2, and the gate oxide integrity characteristics are such that the TZDB high C mode pass rate≧90% and the TDDB pass rate≧90%.
However, although methods for manufacturing wafers free of crystal defects are disclosed in Patent Documents 1 to 3, the wafer characteristics required by IGBT are not clearly indicated. In addition, since it was necessary to make considerable changes to the rotating speed of the quartz crucible and rotating speed of the crystal from the conditions of the prior art in order to grow crystals with defect-free CZ silicon in which the interstitial oxygen concentration was 7×1017 atoms/cm3 or less and the variation in the resistivity within a wafer surface was 5% or less, the margin of the pulling speed enabling growth of defect-free crystals became smaller, thereby resulting in the problem of decreased yield.
In consideration of the aforementioned circumstances, an object of the present invention is to provide a method for manufacturing a silicon single crystal wafer for IGBT and a silicon single crystal wafer for IGBT that enables the margin of the pulling speed to be increased while also enabling the production of wafers having little variation in resistivity.
Patent Document 1: Japanese Unexamined Patent Application, First Publication No. 2001-146496
Patent Document 2: Japanese Unexamined Patent Application, First Publication No. 2000-7486
Patent Document 3: Japanese Unexamined Patent Application, First Publication No. 2002-29891